Advanced CMOS and memory technologies are becoming more structurally complex. The integrated complexity of semiconductor processes and patterning schemes will drive a new era in advanced model-based process control that links advanced metrology and inspection results with advanced process and equipment-level controls.
Traditional process yield-ramp activity has been aimed at reducing the variation of all individual steps of the process. However, each of these individual processes and their associated control parameters have developed quite differently, resulting in unique opportunities to use some processes to compensate for uncorrectable variations arising from other processes. This improvement will not rely on static process adjustments, but on active control of many processes in real time. 3D process modeling (“virtual fabrication”) will be needed in order to deliver control information for state-of-the-art processes during manufacturing. These 3D models will aggregate all of the measured variation from prior processing into a silicon-accurate prediction of the current state of the critical device structures on each wafer. Using computational methods to form this prediction on multiple critical design features at multiple locations on every wafer will enable a new level of feed-forward process control using the newest controls being deployed on process equipment today. This type of 3D model-based process control will be especially critical to the processes and structures where metrology is able to provide only partial information on the nature of variations, which is often the case in these advanced, next generation device structures. Attendees at this discussion will gain an understanding of high-speed 3D process modeling and how model-based process control can be used to improve process yield of advanced semiconductor technologies.