The announcement of a 5nm silicon chip using horizontal gate-all-around transistors in 2017 is just one more indication that the industry will continue some form of traditional scaling combined with 3D architectures as long as it possibly can. Along with this scenario we also see a type of scaling enabled by 3D IC technologies such as die stacking and the stacking of very small geometry wafers. Additionally, interconnect scaling will continue to be utilized. This session will provide an update on the evolution of scaling and discribe how the various players (foundry, IDM, fabless, and application developers) are jockeying for a leadership position with respect to innovation.
Scaling Every Which Way!
Moscone South, TechXPOT South Thursday, July 12 2:00pm to 4:00pm
Do you want to attend this session? Register for SEMICON West.
Vice President, Marketing & Business Development, Metal Deposition Products
PhD, Distinguished Member, Technical Staff
PhD, Corporate Vice President, Advanced Technology Development
PhD, Director, Technology Development and Applications, Metrology Group