The Future of Contamination Control in the Next Generation Supply Chain for Beyond 14nm Node Semiconductor Processes

Tuesday, July 11 2:10pm

New challenges and opportunities in process and design continue to emerge in parallel to ever shrinking semiconductor device geometries.  While Moore’s Law is driving scale reduction, the industry is facing ever-increasing process sensitivity, integration challenges of new materials and the need for unprecedented purity at process maturity.  Today, with such increased process sensitivity and complexity, the industry is redefining on-wafer defect tolerance. The “total” wafer environment contamination characterization and control are essential for yield enhancement with regards to incoming defects to ensure the success of the latest technology nodes.   Due to the increasing number of new materials, device architectures, and cleaning formulations, the severity of killer defects is rising and can remain undetectable without early intervention or safeguards in place. The key is to maintain process stability while controlling contamination.  It is critical to correlate wafer defects to the wafer environment itself, and to define the control limits for gases, chemicals, air, precursors, ultrapure water and substrate surface cleanliness. To deliver these results, it is imperative to have improved defect detection and characterization metrology as well as stringent quality control in the delivery systems for these process materials. Many challenges are associated with detecting these contaminants, but a critical focus must be on early detection to avoid catastrophic failure in the final wafers and finished devices.  This presentation provides an overview of semiconductor manufacturing contamination/defect sources and introduces an approach to enable global collaboration for advanced technology yield enhancement.  The presentation will focus on end users’ and supply chain partners’ perspective on the critical roles of chemicals, advanced filtration and purification, chemical delivery systems and equipment manufacturing as sources of wafer-contamination. It will also highlight the expectation towards utilizing proactive collaborations for contamination control and establishing the critical measurement standards for next generation contamination sources throughout the semiconductor industry supply chain partners, both of which are important in enabling HVM (High volume manufacturing) beyond 14 nm nodes. 

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