2016 was the year when EUV turned the corner. We are now moving to the next phase of EUV industrialization to support high-volume manufacturing at the 7nm logic node and the mid-10nm DRAM node in 2018/2019. For geometric scaling beyond 7/5nm logic node, the introduction of higher Numerical Aperture (NA) will further extend EUV single exposure resolution to provide the most cost effective way for chipmakers to deal with tighter tolerances at lower resolution.
EUV lithography offers broad economic value to chipmakers, beyond cost reduction achieved by fewer patterning layers compared to multiple patterning. It also shortens the cycles of learning via reduced process complexity, which leads to faster time to market. Fewer multiple patterning layers mean less process complexity and steeper ramp to higher yield. In a full fab, EUV enables higher output. Lastly, it delivers superior electrical properties. Altogether, these EUV benefits drive a significant decrease in total net costs.
Additionally, we will discuss the importance of matching lithographic patterning performance between DUV and EUV scanners to enable seamless integration into our customers’ process flows in a mixed environment. All lithography control methods for optical lithography will also be implemented into EUV to optimize system performance and enable maximum production yield for high-volume manufacturing.
To support the readiness of EUV for the economic benefit of our customers, this presentation will review the latest progress made on productivity and availability, as well as the appropriate infrastructure developments required to enable cost-effective shrink – affirming the readiness and economic viability of EUV for high-volume manufacturing.