In lithography, as in so much else in the semiconductor industry, economic reality remains the final arbiter of technical viability. Whether EUVL will succeed or fails depends more on wafer throughput and the cost of yielding silicon than on the limits of line width that can be achieved. These broad economic forces are familiar to the Semicon audience, but the economics of design are more subtle, and manifest themselves in two primary and inter-related categories: physical IP and on-chip wiring.
It has been known for some time that developing process technology in isolation from design leads to suboptimal results, and this has driven design-technology co-optimization (DTCO), which is now standard practice at leading foundries and IP companies. Even with DTCO, however, the final decision to use a particular piece of lithography equipment for a given step rests with the foundry, not with any designer. As a result, designers need to approach lithography decisions both proactively and reactively.
In addition to DTCO (or as an extension to it), predictive design methodologies can help physical IP providers, EDA companies, and chip design teams learn more about potential impacts of design rules before the rules are finalized and sometimes before any details are known. Similarly, once rules are finalized, it is important to develop optimal solutions incorporating them. For physical IP, the key drivers are standard cell and memory area, yield and performance, while for on-chip wiring considerations include achievable cell density, power and clock delivery, and depth of the metal stack. These properties interact in a design-dependent way, so that, for example, the smallest standard cells may not lead to the smallest chip area. In addition, the costs of developing a solution and the cost of making changes to it are also important considerations. This talk looks at all aspects of the economics of design and shows how they interact with manufacturing economics.