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3D Packaging & Integration (3DP&I) Meetings

San Francisco Marriott Marquis Thursday, July 12
9:00am to 12:30pm

 

The Global 3D Packaging & Integration Technical Committee develops standards for semiconductor devices, including processed wafers, chips, or multi-chip configurations to the next level of integration; either in single- or multi-chip configurations. The Committee will focus on items such as materials needed for 3D applications, including prime silicon and glass wafers, temporary and permanent bonding material, specifications needed for processed wafers and/or chips to enter an integration step, etc. In addition, materials related to the elements of, interconnection schemes, and unique packaging assemblies that provide for the communication link between device and packaging. Also included, will be the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, and flexible electronics technology, and metrologies to support these 3D integration and packaging technologies.

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