The mobile market is driving the semiconductor industry to continue its move to transistor architectures that offer greater performance and power benefits than traditional planar architectures. There is not, however, only one way to achieve the required performance. IC manufacturers are pursuing different strategies including leveraging innovations in design rules. To continue the pace of development below 20nm, however, the industry will need to find suitable new channel materials and processes (e.g., MOCVD). This session will present various transistor architecture options below 20nm and the status of channel materials development. Additionally, inspection and metrology challenges associated with new materials will be discussed.        

Main Features and Benefits of 14nm Ultra Thin Body and BOX (UTBB) Fully Depleted SOI (FD-SOI) Technology
 

Michel Haond

FD-SOI Technology Director
STMicroelectronics

Enabling SoC Level Differentiation Through Advanced
Technology R&D

Subramani Kengeri (Biography)

Vice President, Advanced Technology Architecture, Office of the CTO

GLOBALFOUNDRIES

Meeting the Challenges of Next-Generation Scaling

George Gomba

VP, Semiconductor Process R&D

Non-Silicon R&D Challenges and Opportunities
Paul Kirsch, Ph.D.

Director, Front End Processes

SEMATECH

Precision Materials to Meet FinFET Scaling Challenges Beyond 14nm

Adam Brand (Biography)

Director, Transistor Technology Group

Applied Materials

New Approaches to Improving Quality and Accelerating Yield Ramp for FinFET Technology

Joe Sawicki (Biography)

Vice President and General Manager, Design-to-Silicon Division

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