North Hall

3D IC Co-design Challenges: How to Speed 3D IC Deployment

3D-ICs with TSV interconnects are in the early phases of commercialization with the stage set for explosive growth. Image sensors have already ramped to high volume production. Early shipments of memory devices have now started. The advantages of deploying 3D-IC w/ TSV are clear; increased speed, lower power and higher density are the desired outcome. As the industry strives to reach these lofty goals, a few speed bumps have been encountered. One such struggle exists with the design tools that many of us have used for decades. 3D-IC w/TSV now requires additional attention to detail for semiconductor design and fabrication through package design and fabrication. This session will explore these new requirements and the issues that we’ve encountered that are slowing the successful adoption of high volume heterogeneous IC stacks.

2:00pm–2:05pm

Welcome
Session Moderator: Sung Kyu Lim (Biography)
Associate Professor
Georgia Institute of Technology

2:05pm–2:25pm
 

3D/TSV – By Design
(Presentation in PDF)
Mary Olsson (Biography)
Chief Analyst
Gary Smith EDA

2:25pm–2:45pm
 

3D Planning and Prototyping Makes a Difference
(Presentation in PDF)
Ravi Varadarajan (Biography)
Atrenta Fellow
Atrenta

2:45pm–3:05pm
 

Enabling 3D-IC Silicon Realization
(Presentation in PDF)
Samta Bansal (Biography)
Senior Product Marketing Manager
Cadence Design Systems

3:05pm–3:25pm
 

Robust Verificaton of 3D-ICs
(Presentation in PDF)
Carey Robertson (Biography)
Director of Product Marketing
Mentor Graphics Corporation

3:25pm–3:50pm
 

Reliability
(Presentation in PDF)
Craig Hillman
CEO and Managing Partner
DfR Solutions

3:50pm–4:15pm
 

Multi-core 3D Processors
(Presentation in PDF)
Sung Kyu Lim (Biography)
Associate Professor
Georgia Institute of Technology

4:15pm–4:30pm
 

Closing Remarks, Future Requirements and Issues
(Presentation in PDF)
Herb Reiter (Biography)
EDA Interest Group Chair
Global Semiconductor Alliance (GSA)